USB_VBUS=VBUS_SIGNAL_LOW_OR_I, USB_EPD=PULL_DOWN_DISCONNECT, USB_EPWR=POWER_SAVING_MODE_S, USB_ESEA=RESERVED, USB_AIM=GOING_LOW_WITH_FULL
Pin configuration register for pins USB1_DM and USB1_DP
| USB_AIM | Differential data input AIP/AIM. 0 (GOING_LOW_WITH_FULL): Going LOW with full speed edge rate 1 (GOING_HIGH_WITH_FULL): Going HIGH with full speed edge rate |
| USB_ESEA | Control signal for differential input or single input. 0 (RESERVED): Reserved. Do not use. 1 (SINGLE_INPUT): Single input. Enables USB1. Use with the on-chip full-speed PHY. |
| USB_EPD | Enable pull-down connect. 0 (PULL_DOWN_DISCONNECT): Pull-down disconnected 1 (PULL_DOWN_CONNECTED): Pull-down connected |
| RESERVED | Reserved |
| USB_EPWR | Power mode. 0 (POWER_SAVING_MODE_S): Power saving mode (Suspend mode) 1 (NORMAL_MODE): Normal mode |
| USB_VBUS | Enable the vbus_valid signal. This signal is monitored by the USB1 block. Use this bit for software de-bouncing of the VBUS sense signal or to indicate the VBUS state to the USB1 controller when the VBUS signal is present but the USB1_VBUS function is not connected in the SFSP2_5 register. The setting of this bit has no effect if the USB1_VBUS function of pin P2_5 is enabled through the SFSP2_5 register. 0 (VBUS_SIGNAL_LOW_OR_I): VBUS signal LOW or inactive 1 (VBUS_SIGNAL_HIGH_OR): VBUS signal HIGH or active |
| RESERVED | Reserved |